Semiconductor chips or dies are typically manufactured from a semiconductor material such as silicon, germanium, or gallium/arsenide. The dies also typically include terminals to facilitate electrical connection of the die with another electrical component. One common package design includes a semiconductor die attached to a small circuit board, e.g., via an adhesive. Some or all of the terminals of the semiconductor die may then be electrically connected to a first set of contacts of the board, e.g., by wire bonding and/or flip chip technology. At least a portion of the connected board and die may then be encapsulated in a sealing compound to add structural integrity and/or protect portions of the die and board from environmental factors. Often a second set of contacts carried on an outer surface of the board remain exposed. These exposed contacts are electrically connected to the first contacts, allowing the features of the semiconductor die to be electrically accessed.
FIG. 1 schematically illustrates a conventional die and circuit board assembly 1. This assembly 1 includes a semiconductor die 10 having a top surface 22a and a bottom surface 22b. The bottom surface 22b is attached via an adhesive 46 to a circuit board 40. The first surface 22a of the die 10 includes multiple terminals 30, which are used to electrically connect the die 10 to contact pads 42 on the circuit board 40 using wires 44. Typically, dies 10 are manufactured using an etching process (e.g., isotropic etching) and the terminals 30 are distributed across the first surface 22a of the die 10 providing a two-dimensional array of terminals 30.
As semiconductor dies 10 are made smaller, it can be necessary to make the terminals 30 smaller and/or decrease the pitch of the terminals 30 (e.g., reduce the distance between the centers of the terminals 30). Because of limitations on the etching process (e.g., the accuracy or precision of the process), the effective bonding area of the terminals 30 can be greatly reduced when decreasing the size and/or decreasing the pitch of the terminals 30. The same size/pitch limitations occur on circuit boards 40, as the size of the circuit boards 40 is reduced. For example, the spacing required between the contact pads 42 on the circuit board 40 to provide structural support and to ensure proper physical and electrical separation between the contact pads 42 in a two-dimensional array can reduce the effective bonding area to 58 microns for a contact pad pitch of 140 microns. In many cases this effective bonding area is too small to bond the wires 44 to the contact pads 42 and a larger effective bonding area is desirable. A solution to these kinds of reduction in effective bonding area is to replace the etching process with a semi-additive process for producing circuit boards 40 and/or an RDL process for producing dies 10. These processes, however, are more complex and more expensive than the etching processes currently used.